Ex parte GAMBINO et al. - Page 4


          Appeal No. 1999-2115                                                        
          Application No. 08/724,574                                                  


               IV.       Claims 9 through 12 and 15 through 20 under 35               
                         U.S.C. § 103(a) as unpatentable over Yu '534 in              
                         view of Rao.  (Id. at pages 4-5.)                            
               V.        Claim 13 under 35 U.S.C. § 103(a) as unpatentable            
                         over Yu '534 in view of Rao and Tang.  (Id. at               
                         pages 5-6.)                                                  
               VI.       Claim 14 under 35 U.S.C. § 103(a) as unpatentable            
                         over Yu '534 in view of Rao and Morimoto.  (Id.              
                         at page 6.)                                                  
               We reverse these rejections.                                           
               Under 35 U.S.C. § 103, the initial burden of establishing a            
          prima facie case of obviousness rests on the examiner.  In re               
          Piasecki, 745 F.2d 1468, 1471-72, 223 USPQ 785, 787-88 (Fed.                
          Cir. 1984).  In this case, it is our determination that the                 
          examiner has not met the initial burden of proof.                           
               We first consider rejections I through III.  Yu '843                   
          teaches that "good local planarization [of a semiconductor                  
          wafer] can be readily achieved in a CMP process," but "obtaining            
          a complete planarization with good uniformity on the scale of a             
          wafer, or even a die, is not easy."  (Column 2, lines 11-15.)               
          To solve this problem, Yu '843 teaches a method in which, prior             
          to the CMP process, a portion of the wafer surface is modified              


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