Appeal No. 2001-2164
Application No. 09/024,620
It is our view, that the examiner has not established a
prima facie case of obviousness.
Independent claim 1 is very specific as to “a tagged
intervention” response transmitted by a cache. This response is
transmitted by a responding cache to indicate three things:
1. That the responding cache contains a “modified” value,
i.e., a value that has not been written to system memory;
2. That the responding cache “shares” the modified value
with at least one other cache of an adjacent processing
unit; and
3. That the responding cache will “exclusively” source the
value.
Independent claim 11 contains similar recitations. Thus,
three specific requirements are present.
We have reviewed the portions of Singh and Wilson cited by
the examiner and we do not find therein a disclosure or
suggestion of the three claimed requirements. Singh discloses a
Shared (S) coherency state from the MESI protocol. As indicated
at column 9, lines 4-6, when the data is marked “Shared,” this
indicates “that although the cache memory has the latest copy of
the data, other cache memories in the system also have copies of
it.” Accordingly, Singh does appear to disclose a cache that
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