Appeal No. 2001-2530 Page 2
Application No. 09/115,250
BACKGROUND
Appellant’s invention relates to a semiconductor device
including an MOS transistor. An understanding of the invention
can be derived from a reading of exemplary claim 16, which is
reproduced below.
16. A semiconductor device including a MOS transistor
comprising:
a semiconductor substrate;
a gate insulating film on said semiconductor substrate;
a gate electrode in which an amorphous layer having a
grain size of 0.05 µm or less is formed along the surface of
or inside said gate electrode and/or along the side surfaces
of said gate electrode; and
a conductor region which is formed in said
semiconductor substrate by ion implantation after formation
of said amorphous layer.
The sole prior art reference of record applied by the
examiner in rejecting the appealed claims is:
Saida et al. (Saida) 5,866,930 Feb. 02, 1999
(filed Aug. 23. 1996)
In addition, the examiner refers to the following references
in responding to appellant’s arguments:
Hseih 4,688,078 Aug. 18, 1987
Matsukawa et al. (Matsukawa) 5,172,196 Dec. 15, 1992
Jain et al. (Jain) 5,290,727 Mar. 01, 1994
Sandhu et al. (Sandhu) 5,506,166 Apr. 09, 1996
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