Appeal No. 2002-0278
Application 08/797,674
allowing the system to have more than one outstanding request.
See page 2 of Appellants’ specification.
Figure 1 depicts a single node of a multi-node,
multi-processor computer system. Each node can support up to 16
processors 110. These processors 110 are connected to processor
agent chips (PACs) 111. The function of each PAC 111 is to
transmit requests from the associated processors 110 through
cross bar router chips (RAC) 112 to memory access chips (MAC) 113
and then forward the responses back to the requesting processor.
When a processor 110 generates a request to access memory, the
associated PAC 111 sends the request through the proper RAC 112
to a MAC 113. If the request is destined for memory 114 on the
local node, MAC 113 accesses the memory attached to it. If the
request is destined for a memory on another node, MAC 113
forwards the request to TAC 115. TAC 115 is an interface between
the node and SCI ring 116. See page 6 of Appellants’
specification. Figure 2 shows a high level block diagram of the
inventive TAC 200. The table State Machine 203 receives requests
from MAC 113. The table Initialization State Machine 203 will
send the request to the request activation queue 206. The
request will remain in the request activation queue 206 until
2
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