Ex Parte AZADEGAN - Page 4




           Appeal No. 2002-1632                                                                      
           Application No. 08/941,785                                                                


           Appellant further points to Figure 5 of Fujii and asserts that                            
           actually an interpolation circuit is used for error correction                            
           (id.).  Further Referring to figures 6 and 7, Appellant points                            
           out that Fujii selects two adjacent blocks for intrafield                                 
           interpolation if an error block is detected (brief, pages 10 & 11                         
           and reply brief, pages 4 & 5).  Appellant also indicates that the                         
           claims recite coding of image signals by determining a                                    
           mathematical difference between macroblocks based on the                                  
           comparison of one macroblock to another (brief, page 13).                                 
           Additionally, Appellant argues that error flag 102 depicted in                            
           Figure 5 of Fujii, as relied on by the Examiner (answer, page 3),                         
           merely designates an error and is different from the claimed                              
           difference bit that designates whether the coding is based on                             
           macroblock intra-frame coding (brief, page 15).                                           
                 In response to Appellant’s arguments, the Examiner asserts                          
           that the argued features related to coding are not recited in the                         
           claims (answer, pages 4 & 5).  The Examiner further relies on                             
           element 7 of Fujii (col. 3, lines 45-48 and col. 4, lines 17-22)                          
           as an error correction encoding circuit and concludes that the                            
           prior art relates to encoding data (answer, page 5).  The                                 
           Examiner also argues that comparison steps S104-S107, shown in                            
           Figure 7 of Fujii, are the same as the claimed step of                                    

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