Page 5
Appeal No. 2002-1854
Application No. 09/163,874
invention. In re Graves, 69 F.3d 1147, 1152, 36 USPQ2d 1697, 1701 (Fed. Cir. 1995),
cert. denied, 116 S.Ct. 1362 (1996), quoting from In re LeGrice, 301 F.2d 929, 936,
133 USPQ 365, 372 (CCPA 1962). Applying this guidance of our reviewing court leads
us to conclude that the rejection cannot be sustained. Our reasoning follows.
Nakaizumi is directed to a semiconductor memory device having redundant
circuit configuration. As explained in the opening paragraphs, systems existed in the
prior art in which defective memory cells could be replaced by good cells held available
in a bank of redundant cells. The required redundant cells were brought on line by
burning selected fuses. The objective of this reference is to improve upon such prior art
systems.
The examiner does not focus upon the improvement provided by the reference.
In the portion of Nakaizumi to which the examiner refers, the patentee explains that a
plurality of primary word address decoders are arrayed, that six signals are selected for
input to the decoders under different combinations, and that only one is selected and
inputted to a word line W. A concise explanation of the operation of the system is
found in column 7, where with reference to Figures 4 and 6, it is explained that in
normal operation the fuse element 121 (Figure 4) is intact, and the decoder in word line
WJ is in use, but if that decoder becomes defective the system reacts by causing fuse
element 121 to be blown by a laser beam, which causes a decoder from redundant line
WR to be brought into use.
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