Ex Parte YONEMOTO - Page 3



          Appeal No. 2002-1046                                                        
          Application 08/861,831                                                      

          showing an amplifying type solid-state imaging device according             
          to Appellant’s invention.  See page 8 of Appellant’s                        
          specification.  A load capacity element 38 for holding a signal             
          voltage is connected to a vertical signal line 35 through an                
          operation MOS switch 37.  Specifically, the load capacity element           
          38 is connected between the vertical line 35 and a ground                   
          potential, and the operation pulse is applied to the gate of the            
          operation MOS switch 37.  The load capacity element 38 is                   
          connected to the drain of the horizonal switch 39 and the source            
          of the horizonal MOS switch 39 is connected to a horizonal signal           
          line 40.  See pages 11 and 12 of Appellant’s specification.                 
               Independent claim 1 is representative of Appellant’s claimed           
          invention and is reproduced as follows:                                     
               1.  A solid-state imaging device comprising:                           
               a plurality of pixels;                                                 
               a plurality of vertical signal lines connected to said                 
          plurality of pixels;                                                        
               a plurality of horizontal switches disposed at every                   
          vertical signal line, each of said horizontal switches being                
          composed of an insulating gate type FET (field-effect transistor)           
          having first and second main electrodes, said first main                    
          electrode being connected to said vertical signal lines and being           
          formed from first and second drain regions located at opposite              
          sides of a source region of said FET, and FET further having a              
          channel formed in first and second channel directions between               

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