Appeal No. 2003-2108
Application No. 08/881,123
OPINION
We have carefully considered the entire record before us,
and we will reverse the anticipation rejection of claims 1, 2 and
5 through 20.
We agree with the examiner (answer, pages 3 and 4) that
Craft discloses (Figures 4 and 5) a computer system 300 with a
shared address, data and control bus 318 that provides access to
a memory 314 and a bus arbitration control circuit 370 that
determines which of a plurality of devices 344, 348, 360, 362 or
364 is granted access to the shared bus based on priority, and
generates “either an acknowledgment signal to a corresponding one
of the plurality of devices in response to a request generated by
the corresponding device, or the acknowledgment to the
corresponding device according to a predetermined priority order
if more than one request signal is simultaneously generated from
the plurality of devices (see Fig. 4, bus arbitration control
circuit 370; BUS MASTER A[,] 350 BUS MASTER B[,] 352 BUS MASTER C
354; and the respective bus grant lines, as acknowledge signal
for the respective BUS MASTER; col. 11, lines 28-39; col. 14,
line 26 to col. 15, line 60).” The bus arbitration control
circuit 370 subsequently deactivates “the generated
acknowledgment signal if an access actuation signal is
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