Ex Parte Dwork - Page 2



         Appeal No. 2004-0500                                                       
         Application No. 09/488,783                                                 

         consecutive addresses at opposite ends of a range of addresses.            
         Registers which must be frequently read and written are arranged           
         into a third group with assigned consecutive addresses between the         
         addresses of the first and second groups.  According to Appellant          
         (specification, page 2), the register arrangement permits the host         
         processor to access each of the register groups in a single burst          
         transaction.                                                               
              Claim 1 is illustrative of the invention and reads as follows:        
         1.  A method of providing access to registers in a data processing         
         system having registers directly accessible by a host processor,           
         the method comprising the steps of:                                        
              combining into a first group, registers that must frequently          
         be read by the host processor,                                             
              assigning to the registers in the first group, consecutive            
         addresses corresponding to a first end of an address range,                
              combining into a second group, registers that must frequently         
         be written by the host processor,                                          
              assigning to the registers in the second group, consecutive           
         addresses corresponding to a second end of the address range               
         opposite with respect to the first end,                                    
              accessing the registers in the group in a single burst read           
         transfer, and                                                              
              accessing the registers in the second group in a single burst         
         write transfer.                                                            



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