Ex Parte Yu - Page 2




                    Appeal No. 2004-0657                                                                                                                                  
                    Application No. 09/845,604                                                                                                                            


                              The subject matter on appeal relates to a method of                                                                                         
                    fabricating a double-gate vertical channel MOSFET, having separate                                                                                    
                    gates, on a substrate.  The method comprises forming a silicon-                                                                                       
                    insulator stack wherein a silicon fin is capped with insulation,                                                                                      
                    insulating the vertical surfaces of the silicon fin and forming                                                                                       
                    separate gate electrodes on opposing sides of the silicon fin.                                                                                        
                              This appealed subject matter is adequately illustrated by                                                                                   
                    independent claim 1 which reads as follows:                                                                                                           
                              1.   A method of fabricating a double-gate vertical channel                                                                                 
                    MOSFET, having separate gates, on a substrate, comprising:                                                                                            
                              forming a silicon-insulator stack wherein a silicon fin is                                                                                  
                    capped with insulation;                                                                                                                               
                              insulating the vertical surfaces of the silicon fin; and                                                                                    
                              forming separate gate electrodes on opposing sides of the                                                                                   
                    silicon fin, wherein conventional process steps may be thereafter                                                                                     
                    utilized to form the contacts and complete fabrication of the                                                                                         
                    double-gate vertical MOSFET transistor.                                                                                                               
                                                                                                                                                                         
                    The reference set forth below is relied upon by the Examiner                                                                                          
                    in the § 102 and § 103 rejections before us:                                                                                                          
                    Muller et. al (Muller)                                     6,252,284                               June 26, 2001                                      
                                                                                                    (Filed Dec. 9, 1999)                                                  
                              Claims 1-3, 5, 7-11, 13, 14 and 16 stand rejected under                                                                                     
                    35 U.S.C. § 102(e) as being anticipated by Muller.                                                                                                    
                              Claims 4, 6, 12 and 15 stand rejected under 35 U.S.C.                                                                                       
                    § 103(a) as being unpatentable over Muller.                                                                                                           

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