Appeal No. 2004-0748 Page 9
Application No. 09/427,226
The obviousness rejection based on Farnworth and Burns
We will not sustain the rejection of claims 6, 7 and 16 under 35 U.S.C. § 103 as
being unpatentable over Farnworth in view of Burns.
Claim 6 reads as follows:
A method of making a stacked device comprising at least a first integrated
circuit (IC) die and a second IC die, comprising steps of:
(a) building a first IC chip by installing the first die in a first package;
(b) building a second IC chip by installing the second die in a second
package, the second die being identical to the first die, the second package
being internally identical to the first package;
(c) sealing the packages;
(d) modifying the electrical characteristics of at least one of the chips; and
(e) electrically coupling the first chip to the second chip to form a stacked
device.
Farnworth's invention relates to semiconductor devices and associated
integrated circuit configurations and, more particularly, to bare die configurations and
stacked multi-chip (bare die) assemblies with chip-integral vertical connection circuitry
and a method of fabricating such die and assemblies. Farnworth teaches (column 3,
lines 26-45) that:
Each die of the preferred plurality is provided with vias to interconnect with
dice above or below it or a carrier substrate, as the case may be.
Vertically-aligned vias extending from the carrier substrate through each die to
and through the uppermost die comprise a commonly-accessed conductive
vertical pathway from the substrate to each die in the stack for such
commonly-required functions as power, ground, I/O, CAS, RAS, etc. Discrete or
individual vertical pathways for chip-selects extend to each of the various dice, so
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