Appeal No. 2005-1098
Application No. 10/319,149
the examiner has not explained how the proposed modification
where the shield is below the under bump layer 37 could be
accomplished since Kao teaches that the light shield 22 is a
portion of an under bump layer 37 (col. 3, ll. 18-19). The
examiner’s proposed modification fails to account for the
teaching in Kao that the light shield is located so as to block
ambient light from reaching light sensitive portions of the IC
(col. 3, ll. 50-53). Finally, Pernyeszi specifically teaches
away from the proposed modification by teaching that the
application of the shield normally follows the fabrication of the
active elements on the wafer, metallization to form contacts, and
the passivation layer (col. 7, ll. 21-28). We construe this
teaching in Pernyeszi to mean that the shield should be the top
layer over the integrated circuits, metal contacts, and the
passivation layer, contrary to the examiner’s proposed
modification of the Kao structure.
For the foregoing reasons, we determine that the examiner
has not established a prima facie case of obviousness in view of
the reference evidence. With regard to the rejection of claims
10 and 11, we determine that Rhodes has been applied by the
examiner to show the use of chemical-mechanical polishing (CMP)
to planarize a light-shielding structure (Answer, page 4).
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