Ex Parte Mori et al - Page 4



          Appeal No. 2005-0896                                                        
          Application 09/947,125                                                      

          col. 4, lines 27-28 and 47-63; col. 5, lines 27-34 and 59-62;               
          col. 6, lines 48-51).  Within dielectric layer 15 are                       
          electrically conducting layers (17 and 19; figure 6) that may               
          function as signal, power and/or ground layers (col. 4, lines 32-           
          44).  A semiconductor chip (43) is mounted on the thin flexible             
          circuitized substrate using solder joints (45) (col. 8, lines 27-           
          33; figure 10).                                                             
               Angulas does not disclose mounting the semiconductor chip              
          directly on circuitized substrate 13.  However, Melton teaches              
          that in a flip-chip process, such direct mounting is an                     
          alternative to mounting using a carrier (col. 6, lines 14-17).              
          Consequently, the combined teachings of the references would have           
          fairly suggested, to one of ordinary skill in the art, mounting             
          Angulas’ semiconductor chip either by use of a carrier or by                
          direct mounting on circuitized substrate 13.                                
               The appellants argue that Angulas is silent with respect to            
          protection pads and that because Angulas’s chip is on a carrier,            
          Angulas does not have the problem addressed by the appellants of            
          coefficient of thermal expansion mismatch between a semiconductor           
          chip and a substrate on which the semiconductor chip is directly            
          mounted (brief, page 5).  The appellants’ protection pads (9) are           
          copper layers formed either by electroless plating or by adhering           
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