Appeal No. 2006-1303
Application No. 10/000,667
successive instructions and the second memory bank 230 stores a second instruction of the set of
logically successive instructions, the second instruction logically succeeding the first instruction.
The examiner also indicates that fetch unit 116 of Davis constitutes the claimed “read
unit” in communication with the memory such that the read unit addresses a first memory
location during a first clock period and addresses a second memory location during a second
clock period succeeding the first clock period.
We have reviewed the evidence before us, including, inter alia, the disclosure of the
applied references, and the arguments of appellant and the examiner, and we conclude therefrom
that the examiner has not established the requisite prima facie case of anticipation.
We agree with the examiner’s reading of Davis as depicting first and second memories
and a read unit. We also agree with the examiner that the first and second memory banks of
Davis store first and second instructions of sets of instruction.
However, based on the language of the instant claims, the memory (which includes the
plurality of independently addressable memory banks) stores a set of logically successive
instructions.
By contrast, the memory banks 220 And 230 of Davis store separate, independent, sets of
instructions. The memory banks of Davis are not used to store a single set of instructions. It is
true that these memory banks allow for the interleaving of instructions from the memory banks,
but this interleaving permits “simultaneous processing” (column 5, lines 5-10) of two separate
processing engines, each operated by a separate and independent instruction set. It does not
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