Appeal No. 2006-1687
Application No. 10/086,980
The references relied on by the examiner are:
Brent et al. (Brent) 5,459,864 Oct. 17, 1995
Baldwin 6,025,853 Feb. 15, 2000
Claims 1, 3 through 5 and 7 through 35 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Baldwin in view of Brent.
Reference is made to the briefs and the answer for the respective positions of the
appellant and the examiner.
OPINION
We have carefully considered the entire record before us, and we will reverse the
obviousness rejection of claims 1, 3 through 5 and 7 through 35.
We agree with the examiner’s finding (answer, page 3) that “Baldwin teaches a graphics
processor [Figure] (2E) comprising a plurality of parallelized graphics computational units (col.
64, lines 16-21, 25-29 and 38-40), such as, rasterizer, scissor, stipple, alpha test, fog, texture,
stencil test, depth test, local and frame buffer controllers.” We additionally agree with the
examiner’s finding (answer, page 3) that “Baldwin fails to explicitly teach or suggest one or
more task allocation units programmed to bypass defective ones of said subunits within said
groups, and distribute incoming tasks only among operative ones of said subunits.”
With respect to Brent, we agree with the examiner’s finding (answer, page 3) that “Brent
teaches a load balancing, error recovery and reconfiguration control in a data movement
subsystem with cooperating plural queue processors (Fig. 2, abstract, col. 2, lines 39-45, col. 5,
lines 49-52 and col. 6, lines 11-18).” We do not, however, agree with the examiner’s conclusion
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