Appeal 2006-2911
Application 10/005,551
BACKGROUND
Appellants’ invention relates to an arithmetic-logic data processing circuit
that seeks to efficiently execute “basic arithmetic operations” with binary
operands. (Specification 1-3).
Independent claim 1 is illustrative of the invention:
1. A circuit arrangement for adding a first binary operand of N bits and a
second binary operand of M bits, N being greater than or equal to M,
comprising:
an adder adapted to add representative sets of least-significant bits of
the first and second binary operands together to produce a least-significant
bits partial sum and a carryout; and
a multiplexer circuit coupled to the adder and adapted to output a
most-significant bits partial sum by passing one of: a representative set of
most-significant bits of the first binary operand, and an offset of the
representative set of most-significant bits of the first binary operand,
responsive to selection data, the selection data being a function of the most-
significant bit of the representative set of least-significant bits of the first
binary operand.
The following references are relied on by the Examiner:
Daniels 4,203,157 May 13, 1980
Claims 1-19 stand rejected under 35 U.S.C. § 102(b) as being anticipated by
Daniels.1
1 The Examiner has withdrawn the 35 U.S.C. § 112, second paragraph, rejection of
claims 1-19 (Answer 3).
2
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