Appeal 2006-3434
Application 10/687,907
combine Geva or Hale with Miller by incorporating a most recent advanced
load instruction for a check instruction or a specific machine for executing
writing instructions in an architecture for implementing invalid data?
FINDINGS OF FACT
We find that Appellants have elected not to appeal the Examiner’s
rejection of claims 1-3, 6-13, 16-18 under the judicially doctrine of
obviousness double patenting as being unpatentable over claims 1-16 of
Hannum.
Appellants invented a method and system (fig. 3) for preventing
matches of prospective value entries with illegal entries3 in a fully
associative table (206). Particularly, at initialization, a force update
command (203) resulting from a power on condition or a machine specific
instruction populates the associative table (206) with illegal entry values.
(Specification 11). Thus, any subsequent comparison of illegal value entries
in the associative table (206) with prospective value entries received from
check instructions (209) will result in a miss (i.e. no match.) Id.
Miller teaches an architecture (fig.1) for implementing an invalid data
handling least recently used replacement mechanism in a cache memory
system. (Abstract.) Particularly Miller discloses a centrally located address
comparator (ACAM) (104) that contains no valid addresses at initialization
after initializing all valid status bits to an invalid state. As a result, any
comparison of prospective address entries with invalid entry bits in the
ACAM will generate a “miss” in the cache memory. Upon the occurrence
3 Appellants’ Specification, at page 8, attempts to “generally” define illegal
entries as a value which a prospective entry would preferably not acquire in
a normal course of program execution. We find this to fall short of an
express definition, but will adopt it in our discussion above.
4
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