Appeal 2007-0399
Application 09/961,024
Appellants appeal from a Final Rejection of claims 1 to 14, 16 to 18,
28 to 31, 33 to 44, and 49 under authority of 35 U.S.C. § 134. The Board of
Patent Appeals and Interferences (BPAI) has jurisdiction under 35 U.S.C.
§ 6(b).
Appellants’ invention relates to a method and circuit for a multiple
channel communications bus interface to minimize the number of inter-chip
connections. In the words of the Appellants:
Electronic systems and devices are being required to perform
more functions in shorter periods of time. Such electronic systems
and devices contain multiple semiconductor chips, circuits and or the
like. The semiconductor chips or circuits are typically required to
communicate with each other in order to perform particular operations
or functions. To accomplish these communications, multiple
communications links or conductors are required to interconnect the
semiconductor chips or circuits. These electrical connections can
occupy considerable area on a substrate and can also require multiple
pins on each of the chips for the inter-chip communications. Complex
software may also be needed to implement the inter-chip or circuit
communications and to accurately direct or address data signals or
information to various components to perform the particular functions
or operations.
Accordingly, for the reason stated above, and for other reasons
that will become apparent upon reading and understanding the present
specification, there is a need for a multiple channel communications
interface that minimizes the number of inter-chip connects and pins on
each chip. Additionally, there is a need for a multiple channel
communications interface that simplifies the software required for
implementation and minimizes overhead, and is scalable to provide
more or fewer communications channels depending upon design
constraints. (Specification, Page 1)
Claim 1 is exemplary:
1. A communications interface, comprising:
a bus interface coupleable to an internal bus;
2
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