Appeal 2007-1095
Application 09/944,171
BACKGROUND
Appellants’ invention relates to ElectroStatic Discharge (ESD)
protection circuit with very low input capacitance for high-frequency I/O
ports. An understanding of the invention can be derived from a reading of
exemplary claim 1, which is reproduced below.
1. An electrostatic discharge (ESD) protection circuit
with low input capacitance, suitable for an I/O pad, comprising
a plurality of diodes, stacked and coupled between a first power
line and the I/O pad, wherein during normal operation, the
diodes are reverse-biased, and, when an ESD event occurs
between a second power line and the I/O pad, the diodes are
forward-biased to conduct ESD current.
PRIOR ART
The prior art references of record relied upon by the Examiner in
rejecting the appealed claims are:
WATT US 5,623,156 Apr. 22, 1997
JUN US 6,406,948 B1 Jun. 18, 2002
REJECTIONS
Claims 1, 13, 14, 16 and 17 are rejected under 35 U.S.C. 102(e) as
being anticipated by Jun.
Claims 2-4 are rejected under 35 U.S.C. 103(a) as being unpatentable
over Jun.
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