Appeal 2007-1600
Application 09/753,062
With respect to claims 9 and 10, Appellants argue that Kermani lacks
any teaching of a “data structure” or “bit mask,” let alone such an item
indicating which processor is waiting for the lock. We agree that the specific
terms are not present in Kermani. Fig. 2 of Kermani, however, illustrates a
plurality of agents (numbered 1-n), each of which sends a memory access
request to arbiter 102a, which includes a priority encoder 190 (FF 5). A
memory access request by an agent is a digital signal that indicates that said
agent desires access to the shared synchronous memory (FF 6). As is well
known in the art, a priority encoder operates by receiving a plurality of
inputs (bits), and selecting the input having the highest priority. We find that
the set of memory access request signals, taken together, may fairly be
characterized as a “data structure” having a “bit mask” indicating which
processors (agents) are waiting for the lock (i.e., waiting to access shared
synchronous memory). We therefore affirm the Examiner’s rejection of
claim 9, as well as the Examiner’s rejection of claim 10, not separately
argued by Appellants.
With respect to claims 11, 20, and 30, Appellants argue that there is
no express or inherent teaching in Kermani of the use of a release flag to
prevent races between processors between acquisition and release of a lock
(Br. 9). We agree with Appellants. While the section of Kermani cited by the
Examiner (see FF 8) does discuss an “open window” generated when super
agent A is not accessing the shared synchronous memory, there is no
teaching of a “release flag” or any other mechanism in Kermani to prevent
8
Page: Previous 1 2 3 4 5 6 7 8 9 10 Next
Last modified: September 9, 2013