Appeal 2007-1653
Application 10/791,945
Appellants point out that Parolari “describes generally how a control
processor oversees/controls IR processing and how RLC blocks may be
stored in an IR buffer for retransmission, not storage of received punctured
data blocks” (Br. 17) but does not disclose “any other structure that performs
IR processing of received punctured data” (Br. 17).
We agree with Appellants. Paragraph [0112] of Parolari, cited by the
Examiner as teaching the four steps supra, contains general discussion of
incremental redundancy, and mentions soft decision bits, but fails to teach or
suggest the specific operations claimed by Appellants. In response to
Appellants’ Brief filed October 16, 2006, the Examiner attempted to buttress
his holding of anticipation by referring the reader to paragraphs [0051],
[0061], [0074] and [0117] of Parolari as well. While we agree that these
sections do contain general discussion of incremental redundancy (IR)
techniques, none teaches any of the specific steps of configuring, initiating,
accessing or performing which Appellants contest. We have reviewed
Parolari in full and can find no teaching of these specific limitations. Similar
limitations are also present in independent claim 16. Accordingly, we
reverse the rejection of claims 1-7, 9-11, 13-22, 24-26, and 28-31 under
35 U.S.C. § 102.
Claims 8, 12, 23 and 27, each dependent from either claim 1 or claim
16, stand rejected as obvious over the combination of Parolari and Ramesh.
As noted supra, Parolari does not meet the limitations of parent claims 1 and
16. Ramesh fails to teach the elements not present in Parolari. We therefore
reverse the rejection of claims 8, 12, 23, and 27, under 35 U.S.C. § 103.
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