Appeal 2007-2035
Application 09/848,846
STATEMENT OF THE CASE
Appellant invented a method for forming integrated circuitry. In
particular, memory and peripheral circuitry are formed over a semiconductor
substrate. Using a common mask, a halo implant2 is conducted so as to
impart to at least three of the devices three different respective threshold
voltages. To this end, the common masking step involves masking only
portions of some of the devices which receive the halo implant.3 Claim 11 is
illustrative with the key limitation in dispute emphasized:
11. A semiconductor processing method comprising:
a masking step providing a common mask; and
an implant step carried out through the common mask, comprising
conducting a halo implant of devices formed over a substrate comprising
memory circuitry and peripheral circuitry sufficient to impart to at least
three of the devices three different respective threshold voltages, wherein the
common masking step comprises masking only portions of some of the
devices which receive the halo implant, said portions comprising portions of
peripheral circuitry devices.
(Emphasis added.)
2 “Halo implants” are formed in MOSFETs by implanting dopants within a
substrate proximate the source and drain regions, and are typically
underneath the channel region. The implanted halo dopant raises the doping
concentration only on the inside walls of the source/drain junctions, so that
the channel length can be decreased without needing to use a higher doped
substrate. As a result, deleterious effects of “punchthrough” (i.e., merging
of the source and drain depletion regions) are minimized (Specification 2:2-
18)
3 See generally Specification P. 9, l. 1 - P. 10, l. 16.
2
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