Appeal 2007-2467
Application 09/750,150
A. INVENTION
The invention at issue involves a multi-mode predictor in a processor
that predicts non-binary outcome values. Computer execution of an
instruction may depend on a register value from another instruction. Also,
when a computer processor reads values from memory to execute an
instruction, the processor may be first required to calculate a corresponding
memory address. As a result, a delay of execution of instructions may occur
which may adversely affect performance. (Spec. 2).
Appellants invented a processor that selects a mode of prediction and
predicts a value of an instruction based on the selected mode of prediction.
(Id. 5-6). The processor and predictor breaks data dependency between
multiple instructions to increase instruction level parallelism. (Id. 2)
B. ILLUSTRATIVE CLAIMS
Claims 1 and 13, which further illustrate the invention, follow.
1. A method for predicting values in a processor having a plurality
of prediction modes, comprising:
receiving an instruction at a first table;
generating a valid signal from said first table;
providing a prediction mode for said instruction;
determining a hit in a second table, said second table to provide a
prediction value, said hit in the second table being determined according to a
function of said instruction and said first table; and
predicting the predicted value according to said hit and said prediction
mode.
2
Page: Previous 1 2 3 4 5 6 7 8 Next
Last modified: September 9, 2013