Appeal No. 95-1351
Application 07/547,630
for accessing by a load or store instruction, not just the load or store instruction itself. Kane does not
expressly or impliedly disclose a separate prefetch instruction to move a block of data including the
location of memory to be accessed by a load or store instruction.
It is possible that the examiner misapprehends what is meant by latency. Kane describes that
the instruction latency is because "the loaded operand is not immediately available to subsequent
instructions in a processor with an instruction pipeline" (page 1-7) and "[t]he technique used in many
RISC designs to handle this data dependency is to recognize and make visible to compilers the fact
that all load instructions inherently have a latency or load delay" (page 1-8). The latency is a delay
between a load instruction (which loads data from memory into a register) and the time the next
instruction can use the value out of the register. The latency occurs during execution of the
instruction; thus, even if the load instruction is prefetched into cache there will still be a latency during
execution (which time is normally filled by the compiler inserting instructions which do not depend
on the data to be loaded). The claimed prefetch instruction overcomes the latency problem because
the memory address to be accessed by the load instruction has been previously put into the cache by
the prefetch instruction.
To aid in understanding the invention we attach a copy of pages 402-404 from Computer
Architecture A Quantitative Approach by D.A. Patterson and J.L. Hennessy (Morgan Kaufmann
Publishers, Inc., 2d ed. 1996), which discusses compiler-controlled prefetching. This reference is not
prior art. We note that prefetching is not discussed in the first edition.
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