Ex parte PATERSON et al. - Page 3




          Appeal No. 94-3910                                                          
          Application No. 07/966,615                                                  


                                 DECISION ON APPEAL                                   
                                     BACKGROUND                                       
               This is a decision on the appeal under 35 U.S.C. § 134                 
          from the examiner’s rejection of claims 21-28, which                        
          constitute all the claims remaining in the application.                     
          Claims 22-28 ultimately depend from claim 21.                               
               The invention pertains to Erasable Programmable Read                   
          Only Memory (EPROM) semiconductor devices and their                         
          fabrication.                                                                
               Independent claim 21 is reproduced as follows:                         
          21. An array of rows and columns of memory cells                            
          comprising:                                                                 
               a substrate having a first conductivity type;                          
               a plurality of source/drain regions formed in the surface              
          of said substrate, said source/drain regions having a second                
          conductivity type opposite said first conductivity type and                 
          said source/drain regions extending at least between two                    
          adjacent rows of memory cells of said array;                                
               a plurality of field insulating regions formed on a                    
          portion of the surfaces of said source/drain regions;                       
               a plurality of slots etched in said field insulating                   
          regions, said slots exposing the surface of said source/drain               
          regions and extending the length of said source/drain regions               
          and extending at least between two adjacent rows of memory                  
          cells of said array;                                                        


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