Ex parte NAKAO - Page 2




          Appeal No. 95-0634                                         Page 2           
          Application 07/962,322                                                      
          pending.  (Paper 9 at 1.)  We affirm, but we also make a                    
          statement pursuant to 37 CFR § 1.196(c) ("Rule 196(c)").                    
               2.   The application on appeal was filed on 15 October 1992.           
          Appellant claims the benefit pursuant to 35 U.S.C. § 119 of                 
          Japanese patent application no. Hei 3-284551, filed 30 October              
          1991.  (Paper 1, declaration at 1; Paper 6.)  Rohm K.K. is the              
          real party in interest.  (Paper 6.)                                         
               3.   The application is entitled "Semiconductor memory                 
          device with three-dimensional cluster distribution".  (Paper 1              
          at 1.)  The subject matter of the invention "relates to a                   
          nonvolatile memory device, for example, a flash EEPROM (flash               
          electrically erasable programmable read-only memory), in which an           
          insulating film containing metal or semiconductor particles is              
          used in a gate of a transistor."  (Paper 1 at 1.)                           
               4.   The sole claim on appeal defines the subject matter of            
          the invention as follows (Paper 8 at 2, emphasis added):                    
                    2.   A semiconductor memory device comprising:                    
                         a silicon substrate;                                         
                         an insulating layer with a predetermined                     
               width, in which clusters of semiconductor material are                 
               distributed in three dimensions so as to be overlapped                 
               in a direction through the layer;                                      
                         a gate region formed on an upper portion of                  
               said insulating layer; and                                             
                         a source region and a drain region formed in                 
               spaced relation in the substrate beneath said                          
               insulating layer;                                                      
                         wherein said drain region is formed by an                    
               oblique ion implantation, and is overlapped with said                  
               insulating film layer.                                                 







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