Appeal No. 95-3497
Application 08/158,649
the input 8-bit offset-128 binary value (col. 16, lines 8-13).
Also, when SPLIT is true, the AND gate 454 is disabled, thereby
disconnecting carry-out terminal CO of adder circuit 452 from
0
carry-in terminal CI of adder circuit 450. Appellants concede
1
(Brief at pages 3-4) that
given two operands X and Y, the X operand being divided into
sub-operands X1 and X2 and the Y operand being dividable
into sub-operands Y1 and Y2, the device taught by Patti, et
al. computes either [X ±Y ] and [X ±Y ] or X±Y. The choice1 1 2 2
of whether the sums or differences are performed or whether
partial word or whole word operations are performed is
determined by the specific instruction.
The examiner agrees with Appellants that the Patti references do
not disclose "means, responsive to a third instruction, for
generating the difference divided by two of each sub-word in said
X word and the corresponding sub-word in said Y word, the result
thereof determining said corresponding sub-word of said result
word." The examiner maintains that this
feature is old and well known in the art. Moreover, the
common knowledge and common sense of the person of ordinary
skill in the art at the time the invention was made to use
the "difference divided by two" in . . . Patti et al.'s
adder. [Answer at 3.]
The examiner additionally relies on the "well known fact in the
digital computing art that to enable 'divided by two' to be
performed more quickly, a shifter could be used to perform the
desired function" (Answer at 5).
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