Appeal No. 95-3573
Application No. 07/839,704
The disclosed invention relates to a semiconductor memory
cell array that comprises a semiconductor body, a plurality of
bit lines and a plurality of word lines crossing the bit lines to
form a matrix, and at least one semiconductor memory cell
disposed in the semiconductor body at each crossing of the bit
lines and the word lines.
Claim 45 is illustrative of the claimed invention, and it
reads as follows:
45. A semiconductor memory cell array comprising:
a semiconductor body, a plurality of bit lines and a
plurality of word lines crossing said bit lines to form a matrix
and at least one semiconductor memory cell disposal at one of the
cross points of said bit lines and word lines, said semiconductor
memory cell including:
a source region formed with a low resistivity semiconductor
region of a first conductivity type for supplying and retrieving
charge carriers;
a storage region formed with a semiconductor region of said
first conductivity type and disposed separate from said source
region and constituting one electrode of a capacitor for storing
signal charge;
means for forming the other electrode of said capacitor;
a channel region formed with a high resistivity
semiconductor region of said first conductivity type disposed
between said source region and said storage region and adapted
for forming a controllable current path for charge carriers
therebetween, said source, channel, and storage regions being
disposed in said semiconductor body;
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