Appeal No. 95-3573
Application No. 07/839,704
gate means disposed in the neighborhood of said channel
region and substantially surrounding and defining said channel
regions and forming a pn junction therewith for controlling the
potential distribution in said channel region;
said pn junction forming a depletion layer extending into
said channel region to at least nearly pinch-off said channel
region in the absence of bias voltage applied to said gate region
wherein said depletion layer is controllable by the voltage
applied to said source region with respect to said other
electrode forming means;
said source and said storage regions are aligned
substantially perpendicular to the surface of said semiconductor
body;
one of said source and said storage regions is disposed in
the neighborhood of the surface of said semiconductor body and
the other of said source and said storage regions is disposed in
the bulk of said semiconductor body.
The references relied on by the examiner are:
Ishitani 3,982,264 Sept. 21, 1976
Cade 3,986,180 Oct. 12, 1976
Schuermeyer et al. (Schuermeyer) 4,064,492 Dec. 20, 1977
Jenne 4,105,475 Aug. 8, 1978
(effective filing date Oct. 23, 1975)
Harari 4,115,914 Sept. 26, 1978
(effective filing date Mar. 26, 1976)
Clarke et al. (Clarke), Capacitor for Single FET Memory Cell,
IBM Technical Disclosure Bulletin, Vol. 17, No. 9, February 1975,
pages 2579 and 2580.
Junction Field-Effect Transistor Designed for Speedy Logic,
Electronics International Edition, August 19, 1976, pages 4E
and 6E.
Claims 86 and 87 stand rejected under the first and second
paragraphs of 35 U.S.C. § 112 for lack of enablement and for
indefiniteness.
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