Appeal No. 96-0546
Application No. 07/947,010
plurality of switch inputs and a plurality of switch outputs
in response to a plurality of connection requests each
included in one of a plurality of data messages received
separately or simultaneously at said plurality of switch
inputs, said simultaneously active communication paths for
transmitting simultaneously said plurality of data messages to
said plurality of switch outputs;
said requested communication path and said simultaneously
active requested communication paths each comprising a
plurality of data paths for transmitting the data message, and
a plurality of control paths, one of the control paths for
transmitting a clock signal in parallel with the data message,
a first pulse of the clock signal triggering the transmission
of data message bits; and
a clock regeneration circuit at each switch input for
receiving the data message and the clock signal and for
transmitting a realigned data message and clock signal to said
any one of the switch outputs, the clock regeneration circuit
including delay means for adjusting a pulse width of the clock
signal thereby aligning the clock signal and the data message
bits for minimizing skew and pulse distortion between the
clock signal and the data message bits.
The references relied on by the examiner are:
Upp 4,914,429 Apr. 3,
1990
Newman 4,965,788 Oct. 23,
1990
Todd 5,072,442 Dec.
10, 1991
Buhrke et al. (Buhrke) 5,231,631 July 27,
1993
(effective filing date Aug. 15,
1989)
Traw et al. (Traw) 5,274,768 Dec. 28,
1993
(filing date May 28,
1991)
3
Page: Previous 1 2 3 4 5 6 7 Next
Last modified: November 3, 2007