Appeal No. 97-1057
Application 08/160,298
significant bit. Therefore, we sustain the rejection of
claims 2, 3, 43 and 44.
We now consider the rejection of claims 9 and 50 which
are grouped together. Claim 9 depends from claim 1 and
recites that a plurality of data registers receives an input
from the output of the ALU and an input from the output of the
shifter. The examiner has provided a reasonable analysis as
to why the presence of registers, as broadly recited in claim
9, would have been obvious to the artisan in view of the
applied prior art. Appellants argue that Chu does not show
such a register at the output of the shifter, but this
argument fails to address the obviousness of broadly providing
such a register. Appellants also argue that “claims 9 and 50
require storage of both the output of the arithmetic logic
unit and the output of the shifter during the same operation.
Neither Chu et al nor Vassiliadis et al show the claimed
simultaneous storage of these two outputs in any mode” [brief,
page 10]. We agree with the examiner that this argument of
appellants is not commensurate in scope with the claimed
invention. We find nothing in claim 9 which requires the
simultaneous storage as argued by appellants. Since
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