Appeal No. 95-1536
Application 07/746,176
erasing cycle. A high-intensity electric field is formed between the floating gate 28 of memory cell M11
and the substrate 22. Thus, electrons which have accumulated in the floating gate 28 discharge to the
substrate and the drain 42. As a result, the threshold value of the memory cell transistor M11 is shifted
in the negative direction.
In the next cycle labeled M2 (Figure 7), the method is the same except that a 20 volt pulse is
also applied to word line WL1 and the potential of the bit line is transferred to the drain layer of
memory cell M12 through the first selection transistor QS11 and memory cell M11. Similar to memory
cell M11, memory cell M12 is thus erased. The procedure is repeated by sequentially applying the high
level voltages as illustrated in Figure 7 to the various word lines, thereby sequentially erasing the
memory cells of cell block B1 in an order from M11 to M18.
In the data write cycle for memory cell M8 (Figure 9), a high level voltage is applied to control
gate line SG1, rendering transistor QS11 conductive and electrically connecting the cell block B1 with
the bit line BL1. An intermediate level potential voltage is applied to word lines WL1-WL7 while a
high level voltage is applied only to word line WL8. A high intensity electric field is thus formed only
between the floating gate of the selected memory cell M8 and the substrate 22, and a tunnel current
flows therebetween. This process is repeated where a high level voltage is applied sequentially to
memory cells M7-M1 through word lines WL7-WL1, thereby sequentially writing data into each of
these memory cells.
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Last modified: November 3, 2007