Appeal No. 95-1536
Application 07/746,176
Opinion
The Rejection under 35 U.S.C. § 112, First Paragraph:
We will not sustain this rejection. We find no merit to the examiner’s position to the effect that
appellants’ disclosure is not enabling because it does not specifically disclose “means for sequentially
programming selected memory cell transistors…and for sequentially erasing the selected memory cell
transistors in a manner…”. This language is directed to memory address circuitry for providing the
disclosed pulses for addressing the transistor memory array. Circuitry for addressing the cells of
memory arrays are notoriously old in the art, and the examiner has made no specific showing why it
would not have been obvious for one of ordinary skill in the art to make the address circuitry for
producing the pulses disclosed by appellants for operating their memory in the manner disclosed. An
inventor need not explain every last detail of his invention since he is speaking to those skilled in the art
and may rely on the skill in the art to provide the same. DeGeorge v. Bernier, 768 F.2d 1318, 1322,
226 USPQ2d 758, 762 (Fed. Cir. 1985).
The Rejection under 35 U.S.C. § 112, Second Paragraph:
We will not sustain this rejection. We find no merit to the position to the effect that use of the
terms “program” and “erase” render the claims indefinite. Appellants recite programming selected
memory cell transistors in such a manner as to write data. Programming is broadly setting a routine and
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