Appeal No. 96-0609
Application No. 08/024,803
of said memory shift registers (RDM ) of
j
said set having a size of one block of
information and being conected [sic
connected] to the central memory (RAM) so
as to enable, in one memory cycle a
parallel transfer of a block of information
(bi) between said memory shift register and
said central memory, the memory shift
registers of said set of memory shift
registers being independent of each other
for simultaneous shifting of blocks of
information,
a plurality of processor shift registers (RDP1
. . . RDP . . . RDP ) each processor shift registerj n
(RDP ) being each connected to the cache memory (MC )j J
of a processor (CPU ) whereby each processor (CPU )j j
has a dedicated cache memory (MC ) and a dedicated
j
shift
register (RDP ) for parallel transfer of a block of
j
information (bi) between said processor shift
register
(RDP ) and said cache memory (MC ),j j
a set of serial links (LS . . . LS . . . LS ),1 j n
each connecting a memory shift register (RDMj) and a
processor shift register (RDP ) for making a private
j
connection between a paired memory shift register
and
processor shift register (RDM , RDP ) andj j
transferring
at a frequency F of at least 100 megahertz blocks of
information (bi) between the memory shift register
and
the processor shift register (RDM , RDP )j j
autonomously
and independently of other registers and other
serial
links.
The Examiner relied on the following reference:
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