Ex parte PAWATE et al. - Page 2




               Appeal No. 96-1319                                                                                               
               Application 07/934,982                                                                                           



                      This is a decision on the appeal under 35 U.S.C. § 134 from the examiner’s                                
               rejection of claims 1-16, which constitute all the claims in the application.  An amendment                      
               after final rejection was filed on May 18, 1995 and was entered by the examiner.                                 
                      The disclosed invention pertains to a smart video memory for use in a method and                          
               apparatus for video processing.  More particularly, the smart video memory has all the                           
               features of a conventional video memory as well as a processor for executing instructions                        
               on the same integrated circuit.  The smart memory can operate in a standard mode in                              
               which the processor is not used or in a smart mode in which the processor handles some                           
               of the processing requirements of the video processing system.                                                   
                      Representative claim 1 is reproduced as follows:                                                          
                      1.  A smart video memory, comprising:                                                                     
                      data storage including a random access memory and a serial access memory;                                 
                      a processor to execute instructions stored in said data storage and to read and                           
               write data in said data storage, said data storage and processor integrated in a single                          
               integrated circuit;                                                                                              
                      external leads coupled to said data storage and processor and extending from said                         
               single integrated circuit for externally connecting an external device to said data storage                      
               and processor, said external leads arranged such that the smart video memory is directly                         
               accessible as a standard video memory device by said external device while the                                   
               processor is prevented from executing the instructions; and                                                      
                      at least one of said external leads comprising a serial data lead coupled to said                         
               serial access memory for serial data access.                                                                     


                                                               2                                                                





Page:  Previous  1  2  3  4  5  6  7  8  9  10  11  12  Next 

Last modified: November 3, 2007