Appeal No. 96-1983
Application No. 08/222,784
the circuit further comprising:
ii) ABIST means driving said memory means for
providing said memory means with self-test patterns;
iii) data compression means responsive to said ABIST
means and to said memory means for detecting and [sic] address
of at least one of said word lines in said memory means that
is defective; and
iv) fail register means responsive to said ABIST
means and to said data compression means for storing an
address of a defective word line and for generating a number
indicative of the number of defective word lines that exceeds
the number of redundant word lines of said redundant array,
v) said comparator means for comparing the
addresses of said word lines with the addresses of said
defective word lines and for selecting a predetermined word
line of said redundant array;
vi) OR-gate means having inputs for receiving
signals generated by said comparator means and having an
output connected to a latching means; and
vii) AND-gate means having a first input
connected to said latching means and a second input responsive
to signals generated by said data compression means, for
generating a signal at an output thereat which is indicative
of a defective line of said redundant word lines.
The examiner relies on no references.
Claims 1-9 stand rejected under 35 U.S.C. § 112,
second paragraph, for failing to particularly point out and
distinctly claim the invention.
Rather than repeat the arguments of appellants or the
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