Appeal No. 96-3850
Application No. 08/253,480
by the appellant and the examiner. As a consequence of our
review, we will reverse the obviousness rejection of claims 1
through 12.
Claim 1 recites:
. . . a read/writable memory formed in the same
semiconductor chip as the microprocessor and
ordinarily inoperative during the POST, the system
comprising:
(a) a diagnostic interrupt vector table set in
the read/writable memory. (underlining added for
emphasis)
In other words the interrupt vector table set must be located
in a memory that is 1)read/writable, 2)on the same
semiconductor chip as the microprocessor, and 3)ordinarily
inoperative during the POST.
The examiner admits in the rejection (Final Rejection,
page 2) that with respect to Treu, "[n]ot explicitly taught is
the use of an interrupt vector table." The examiner states
(Answer, page 3), "Sato was cited as teaching an interrupt
vector table being set in a read/writable memory." However,
as pointed out by appellant (Brief, page 8), Sato "does not
store the table in a memory formed on the same semiconductor
chip as the microprocessor." The examiner attempts to
overcome this deficiency by citing Siewiorek to illustrate
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