Appeal No. 96-4003
Application 08/288,131
Examiner, in the Answer dated January 24, 1996, withdrew the 35 U.S.C. § 112, second paragraph,
rejection of claims 22, 24, 26, and 31, indicated the allowability of claims 7-10 and 17-20, and allowed
claims 25-31. In addition, the Examiner entered several new grounds of rejection with respect to
claims 1-6, 11-16, and 21-24. In a further response to a Reply Brief filed by Appellants on March 11,
1996, the Examiner, in a Supplemental Answer dated May 29, 1996, withdrew the rejection of claims
22 and 24 and indicated their allowability. Accordingly, this appeal now involves only claims 1-6, 11-
16, 21, and 23.
The claimed invention relates to a circuit and a method for generating a bias for a
semiconductor device. The bias generating circuit includes a plurality of bias circuits responsive to a
different enable signal from a control circuit as illustrated in Figure 1 of the drawings. More particularly,
Appellants indicate at pages 4 and 5 of the specification that, at any particular time, only one of the bias
circuits is enabled by an active enable signal from the control circuit. According to Appellants’
specification, the enablement of only one bias circuit for any operational mode results in a reduction of
power consumption.
Claim 1 is illustrative of the claimed invention and reads as follows:
1. A circuit for generating a bias for a semiconductor device, the circuit comprising:
a control circuit, responsive to a plurality of input signals, for activating only one of N enable
signals at any time, wherein N is greater than one;
a plurality of N bias circuits, each having an output terminal and an enable terminal, the enable
2
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