Appeal No. 1996-4050
Application No. 08/410,375
Judges.
HECKER, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal from the final rejection of
claims 1 through 20, all of the claims pending in the
application.
Appellants’ invention relates to a logic array integrated
circuit structure including complementary MOS field effect
transistors (P-channel and N-channel) and bipolar transistors,
referred to as a BiCMOS logic array. This logic array
structure is more compact and flexible than the prior art in
conserving layout patterns for the conducting lines which
interconnect to transistor devices. In particular, as shown
in Figure 3, a repeating cell structure has three vertical
regions or columns with a first columnar region designated N-
CHANNEL, a second columnar region designated P-CHANNEL and a
third columnar region designated BIPOLAR. The transistors in
the N-channel columnar region form eight NMOS transistors in a
P-well region of the substrate. The transistors in the P-
channel columnar region form eight PMOS transistors in a N-
2
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