Appeal No. 1996-4050
Application No. 08/410,375
well region of the substrate. And, two bipolar transistors
are formed in the bipolar column. Representative
claim 10 is reproduced as follows:
10. In a repeating BiCMOS logic gate array integrated
circuit structure in a semiconductor substrate, said substrate
having first and second columnar regions, said first columnar
region of a first conductivity type and said second columnar
region of a second conductivity type, each of said columnar
regions having active regions with gate electrodes vertically
separating said active regions into source/drain regions, the
improvement comprising:
a third columnar region of said first conductivity type,
said third columnar region having a collector, base and
emitter region of a first bipolar transistor and a collector,
emitter and base region of a second bipolar transistor, said
regions aligned vertically in said third columnar region and
aligned with respect to said gate electrodes and said
source/drain regions of said first and second CMOS regions;
whereby a macrocell can be formed from said first, second
and third columnar regions with a grid of vertical and
horizontal routing tracks over said columnar regions, no
matter what order said columnar regions are located
horizontally adjacent to each other.
No references are relied upon by the Examiner.
Claims 1 through 20 stand rejected under 35 U.S.C. § 112,
first paragraph, as not supported by an enabling disclosure.
Rather than repeat the arguments of Appellants or the
Examiner, we make reference to the brief, reply brief and the
answer for the respective details thereof.
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