Ex parte BALMER - Page 5




          Appeal No. 96-4184                                                          
          Application No. 08/159,346                                                  


               In claims . . . 65, 66 . . . the plurality of data                     
               registers are connected in one loop and the normal                     
               read and write operations include plural bits within                   
               the single loop.  Meltzer states at column 8, lines                    
               54 to 59:                                                              
                    "The shift register loops on the pages of                         
                    the file are rotated synchronously, in the                        
                    direction shown by the arrows, both with                          
                    respect to loops within a page an [sic,                           
                    and] with respect to loops in different                           
                    pages so that all bits constituting Bytes K                       
                    in Pages 1-N appear at read/write ports 21,                       
                    22, 23, . . . and 2N at the same time."                           
               This portion of Meltzer clearly teaches plural                         
               loops.  In addition, this portion of Meltzer further                   
               teaches that the read/write operations occur                           
               simultaneously in all the loops.  Thus Meltzer                         
               cannot write to or read from plural bits of data                       
               within a single loop as required by the recitations                    
               of claims . . . 65, 66 . . . .                                         
               Meltzer clearly states (column 8, lines 39 through 46)                 
          that each of the Loops 1 through M is configured as a single                
          shift register loop (Figure 1), with each loop having 4,096                 
          bit storage positions (i.e., Bit 0 to Bit 4,095).  We agree                 
          with appellant that Meltzer discloses "plural loops" of shift               
          registers, and not "a loop" of registers as claimed.  The                   
          plurality of shift register loops in Meltzer are connected in               
          parallel for reading or writing of an M-bit byte, and all of                



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