Ex parte LIOU et al. - Page 2




               Appeal No. 97-0557                                                                                                     
               Application 08/371,040                                                                                                 


               from the Examiner's final rejection  of claims 13 through 17,2                                                               
               all the pending claims in the case.                                                                                    
               The disclosed invention pertains to an architecture                                                                    
               for distributing input signals from a bondpad area to an                                                               
               interior portion of an integrated circuit device, such as a                                                            
               plurality of memory blocks.  Instead of placing input buffers                                                          
               at the periphery of the integrated circuit device, the claimed                                                         
               invention distributes the unbuffered input signal lines to the                                                         
               input buffers located in the interior portion of the                                                                   
               integrated circuit adjacent the circuit blocks that use the                                                            
               input signals.                                                                                                         
                       Representative claim 13 is reproduced as follows:                                                              
                       13. An input architecture for supplying a plurality of                                                         
               signals to a plurality of circuit blocks located in an                                                                 
               interior portion of an integrated circuit device, comprising:                                                          
                       a bondpad area;                                                                                                
                       a plurality of input buffers each located adjacent to and                                                      
               connected to one of said plurality of circuit blocks;                                                                  
                       a plurality of unbuffered signal lines, each of said                                                           
               plurality of unbuffered signal lines connected between said                                                            
               bondpad area and all of said plurality of input buffers.                                                               


                       2An amendment after the final rejection was filed on                                                           
               April   23, 1996 [paper no. 30] and entered in the record.                                                             
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