Appeal No. 1997-1185
Application No. 08/497,845
DECISION ON APPEAL
This is a decision on appeal from the final
rejection of claims 1 through 19, all claims pending in this
application. The invention relates to a method for
designing clock wiring in, for example, a Large Scale
Integrated Circuit (LSI). The invention is based on the
recognition that a shorter clock period can be established if
one ignores the conventional rule of providing a zero clock
skew between clock nets. In particular, looking at Figure 4,
if a 2 nanosecond delay gate 217 is inserted between clock
driver 202 and flip-flop 205, causing a 2 nanosecond skew
between the clock nets to flip-flops 204-206, a clock period
of 8 nanoseconds can be employed instead of a clock period of
10 nanoseconds which would have been mandated by the delay of
the worst case path. To shorten the clock cycle, the
invention evaluates delay time margins for a plurality of
paths (in this case, a zero delay time margin for path 215 and
a 4 nanosecond delay time margin for path 216), detects a
worst case path (path 215), calculates a clock skew adjusting
time by determining a difference between the delay time margin
of a secondary worst case path (4 nanoseconds of 216) and the
2
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