Appeal No. 97-1694
Application 08/351,064
bus terminal Z and corresponds to appellants' figures 27 and
29. Figure 3 is not meaningful when there is no signal on the
bus Z because no signal represents a high impedance condition
at Z, not zero volts at Z as argued. In any case, claim 41
says nothing about there being no signal on the bus.
Therefore, we find appellants' arguments unpersuasive.
Nevertheless, we find that the claim limitation at issue
is not taught by IBM. The threshold voltage of the NMOS
device is the voltage between 0 and the point where the upper
curve departs upward from the horizontal axis. The threshold
voltage of the PMOS device is the voltage between the point
labeled Vdd (where the bus voltage at Z equals Vdd) and the
point where the lower curve departs downward from the
horizontal axis. The difference between the termination
voltage Vdd and the lower voltage line (ground) is the voltage
between 0 and Vdd. By inspection, the sum of the threshold
voltages is not greater than the difference between the
termination voltage and ground; the curves would have to
overlap along the horizontal axis for this to be true as shown
in appellants' figure 27. While it would have been possible
to operate the circuit in IBM to meet this condition by
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