Appeal No. 97-2630
Application 08/186,050
claim 1. Claim 1 does not recite anything regarding the
separation of V lines for buffers or the isolation of power
ss
supplies.
For the foregoing reasons, the rejection of claim 1 as
being unpatentable over Duschatko is sustained.
Claim 15 recites an integrated circuit comprising
internal circuitry, buffers, and a first set of V leads
ss
connected to the internal circuitry and a second set of Vss
leads connected only to the buffers. In light of the
appellant’s specification (see for example pages 1-3), it is
understood that “buffers” means output buffers. Also,
evidently according to the appellant, “internal circuitry”
means the remaining circuitry on the integrated circuit chip
other than the buffers. (See Reply Brief at page 3, lines 19-
20). The examiner states that Duschatko does not disclose
separate V connections as claimed but that such a limitation
ss
would have been obvious based on well-known design guidelines.
The evidence the examiner provided in support of his finding
of well-known design guidelines, however, does not support the
obviousness conclusion. The examiner cited Fujita as teaching
separate V ground connection limitations, without a
ss
9
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007