Appeal No. 97-2630
Application 08/186,050
meaningful explanation. (Examiner’s Answer at page 5). It is
not known what in Fujita the examiner regards as separate Vss
leads to the internal circuitry and to buffers.
As is defined in appellant’s specification, V means
ss
general digital ground. (Specification at page 9). While the
portion of Fujita cited by the examiner teaches making
separate ground connections to digital and analog circuits on
an integrated circuit chip (column 6, line 63 to column 7,
line 8), it is not seen how that would have suggested one set
of ground leads exclusively for output buffers as is required
by claim 15. The examiner has not pointed to any disclosure or
suggestion of an integrated circuit chip containing both
digital and analog circuits and the only digital circuits of
which are comprised of output buffers. That teaching would
have been necessary to combine with what Fujita shows to
arrive at the appellant’s claimed invention. Even if the
prior art may be modified in the manner suggested by the
examiner does not make the modification obvious unless the
prior art suggested the desirability of the modification. In
re Fritch, 972 F.2d 1260, 1266 n.14, 23 USPQ2d 1780, 1783-84
n.14 (Fed. Cir. 1992).
10
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007