Appeal No. 1997-0556
Application No. 08/286,265
BACKGROUND
The appellants' invention relates to a N-way set-associative cache memory which
includes a store hit buffer for improved data access. The store hit buffer recognizes when
the processor requests data stored in the buffer and substitutes the buffered data for data
from the memory array. An understanding of the invention can be derived from a reading
of exemplary claim 19, which is reproduced below.
19. An N-way, set associative cache memory comprising:
a memory array having N sets of data bit lines and N sets of
associated address tag bit lines;
an addressing circuit which generates a tag compare address and a
set address for a read operation, and write control signals for a write
operation;
N amplifier circuits, each of which is coupled to corresponding sets of
the data/address tag bit lines of the memory array, each of the N amplifier
circuits having outputs which provide data and address tags sensed from the
respective data/address tag bit lines of the memory array;
N read/write (R/W) circuits, each of which is correspondingly coupled
to the outputs of the N amplifier circuits and also to the addressing circuit,
each of the R/W circuits comprising:
a buffer circuit for buffering write data/address information
preceding a write operation, the buffer circuit including a comparator which
generates a set compare result when the set address matches the write
address;
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