Appeal No. 1997-0556
Application No. 08/286,265
at page 9.) We agree with appellants that the language of the independent claims 19, 24,
and 29 expressly set forth limitations to the read/write buffer in the cache memory which
solve this problem. The examiner repeatedly cites to the same portions of Rosich and
maintains that skilled artisans would have been motivated to incorporate the read/write
buffer for main memory read conflicts into the cache memory to address read conflicts
therein. (See answer at pages 8-20.) We do not agree with the examiner. Appellants
argue that Rosich was aware of cache memories since a cache memory is included in the
system of Rosich, but the read/write buffer was not included into the cache memory.
Therefore, if the inclusion of the read/write buffer and substitution were as apparent as the
examiner implies, then Rosich would have similarly included such a feature in the cache
memory. (See brief at pages 10 and 11.) On its face, we agree with the appellants’
rationale rather than the examiner’s unsupported conclusion, which in our view uses
hindsight in an attempt to reconstruct the claimed invention. The examiner has not
provided any cogent line of reasoning for skilled artisans to extend the teachings of Rosich
with respect to main memory to another subsystem therein which does not teach or
suggest a need for this additional savings with respect to a clock signal. Therefore, we
cannot sustain the rejection of independent claims 19, 24, and 29 and their respective
dependent claims.
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