Appeal No. 1997-3161
Application No. 08/450,553
The claimed invention relates to a method of erasing the
memory cells of an electrically erasable programmable read-
only memory, commonly referred to as an EEPROM. More
particularly, Appellant indicates at pages 8 through 10 of the
specification that a first voltage higher than both the supply
voltage and the ground voltage and a second voltage lower than
both the supply voltage and ground are generated. During the
erasing operation, the first generated voltage is applied to
the control gate of a nonvolatile storage transistor of a
memory cell, while the second voltage is applied to either the
source or the drain.
Claim 43 is illustrative of the invention and reads as
follows:
43. A method of erasing an EEPROM memory cell supplied
with a supply voltage and a ground voltage, the EEPROM
memory cell comprising a storage transistor including a
substrate having a first conductivity type and provided
therein with a source and a drain each of a second
conductivity type, a floating gate disposed over the
substrate and a control gate disposed over the floating
gate, said method comprising steps of:
applying a first voltage higher than both the supply
voltage and the ground voltage to the control gate; and
applying, at least partially concurrently with the
application of the first voltage, a second voltage lower
than both the supply voltage and the ground voltage to at
3
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