Appeal No. 1997-3442 Page 3
Application No. 08/210,288
a third control gate line coupled to at least control
gates of said third selection transistors;
a fourth control gate line coupled to at least control
gates of said fourth selection transistors.
The examiner relies on the following references:
Choi et al. (Choi) 4,962,481 Oct. 9,
1990
E. Adler, “Densely Arrayed EEPROM Having Low-Voltage Tunnel
Write”, IBM TDB, Vol. 27, No. 6 pp. 3302-3307, Nov. 1984
Japanese Patent Application
Kanazawa 2 02-74069 Mar. 14, 1990
Claims 1, 3, 4 and 6 through 8 stand rejected under 35
U.S.C. 102(b) as anticipated by Adler. Claims 2, 5 and 9 stand
rejected under 35 U.S.C. 103 as unpatentable over Adler in view
of either one of Choi or Kanazawa.
Reference is made to the briefs and answer for the
respective positions of appellants and the examiner.
OPINION
At the outset, we note our displeasure with the way the
examiner sets forth the rejection in the answer. M.P.E.P. 1208
2Our understanding of this reference is based on an
English translation thereof prepared by the United States
Patent and Trademark Office. A copy of this translation is
attached hereto.
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